1. Field of the Invention
The present invention relates to a semiconductor device and a layout design method for the semiconductor device, and in particular to a semiconductor device and a layout design method for the semiconductor device that arrange dummy gates in order to control fluctuation in shapes of gate electrodes of transistors.
2. Description of the Related Art
There is known a layout design method of arranging dummy gates in positions a fixed distance apart from gate electrodes of transistors such that gate patterns are arranged at equal intervals in order to control fluctuation in shapes of the gate electrodes of the transistors. JP-A-2000-200882 (FIG. 1) and JP-A-2000-223663 (FIG. 1) described below mention that the dummy gate is formed in a process identical with that for a gate electrode of an adjacent transistor, has an composition and a shape identical with the gate electrode, and is floating in terms of a potential, connected to a power supply potential, or grounded.
In addition, a JP-A-2002-26125 (FIG. 1) mentions that all gate patterns are formed to match a gate electrode having a longest active region.
However, when layout design is performed to arrange a dummy gate between transistors such that gate patterns are arranged at equal intervals, compared with the case in which a dummy gate is not arranged, a man-hour for arranging the dummy gate and design rules, which should be considered because of the arrangement of the dummy gate, increase. Thus, it is possible that a layout design man-hour and at area increase.
For example, as a layout design method, it is conceivable to adopt a design method of arranging transistors and dummy gates in advance such that gate patterns are arranged at equal intervals and performing a wiring step after that. However, when such layout design is performed, in particular, in a semiconductor device like a memory for which a layout has to be designed within a fixed pitch width or, for example, in order to perform layout design taking into account a yield such as an arrangement of two contacts, it may be inevitable to increase an area in a vertical direction of a pitch width to keep gate patterns within a predetermined pitch width because of restriction of design rules among the gate patterns. In the worst case, it may be inevitable to rearrange the transistors and the dummy gates to repeat the design.
Specifically, the problems will be explained with layout design for a latch circuit shown in FIG. 33 as an example. Here, in order to explain the problems plainly, a layout structure is shown and explained only for an area 33(A) surrounded by a dotted line.
FIG. 34 is a layout in which transistors in the area of 33(A) in FIG. 33 are arranged in a state in which the transistors share source/drain regions as much as possible and dummy gates are arranged to match a largest gate width of gate electrodes provided in the transistors.
Here, pt1 is set as a pitch width in an x direction in the figure that is determined in advance because of design restriction. NW indicates an N-WELL region and other parts are assumed to be a P-WELL region. D_NW and D_PW are active regions that are arranged on N-WELL and P-WELL and used for fixing respective regions in a substrate at a power supply potential or a ground potential. DC indicates contacts.
TR1 to 4 are transistors and GA1_1 to GA1_4, GA2_1 to GA2_2, GA3_1 to GA3_4, and GA4_1 to GA4_2 are gate electrodes on the transistors TR1 to 4. EXT_GD is a length of projected parts to the outside of the active region of the gate electrodes.
Dummy gates DG30, 31 connect gate patterns, which are formed to be arranged in parallel with the gate electrodes on TR1 to 2, and TR 3 to 4 (in a y direction in the figure) and over a region including the projected parts in a gate width direction of all the gate electrode (in the y direction in the figure). Here, an interval in a gate length direction (an x direction in the figure) between gate patterns of the dummy gates and between the gate electrodes and the dummy gates is a fixed space SP_GA_L. The interval is set to a predetermined length that prevents fluctuation in shapes of the gate patterns. In addition, a width in a gate length direction of the respective gate patterns of the dummy gates (the x direction in the figure) is a minimum gate length LG_min of the gate electrodes.
As shown in FIG. 34, when a transistor has plural gate electrodes with different gate widths, a dummy gate is formed on an extended line in a gate width direction of the gate electrodes. For example, the gate electrode GA1_2 has a small gate width compared with the gate electrode GA1_1 and it is necessary to arrange gate patterns over both ends in a gate width direction of the gate electrode GA1_1. Thus, a dummy gate is formed in a position a minimum spacing SP_GA_min apart from the gate electrode GA1_2 in the gate width direction (in the y direction in the figure) between the gate patterns as encircled by (A1).
As opposed to FIG. 34, FIG. 35 is a diagram in which contact regions for connecting with the gate electrodes are formed and wired using one-layer metal M1. CGMA20 to 28 are regions in which contacts for connecting a gate layer and a metal layer are arranged, which are herein after referred to as gate contact regions. SP_M1_min is a minimum spacing rule of the one-layer metal.
In usual layout design, in particular, layout design for a memory, wiring is made by one-layer metal as much as possible. Metal wiring layers of a second layer and upper layers are often used for global wiring for propagation in a long distance such as a power supply wiring and a clock. In this example, wiring by the one-layer metal is performed as much as possible. However, CGMA20 and CGMA21 as well as CGMA24 and CGMA25 cannot be connected unless two-layer metal is used because of restriction of wiring by the one-layer metal.
In (A2) to (A6) encircled by an alternate long and short dash line, the gate contact regions CGMA20, 23, 24, 26, and 28 and the dummy gates DG30 and 31 are required to be arranged complying with the spacing rule SP_GA_min between gate patterns. In (A7) and (A8), the gate contact regions GCMA22 and 23 as well as the gate patterns connecting CGMA27 and CGMA28 are required to be arranged complying with the spacing rule SP_GA_min between gate patterns. In (A9) and (A10), the gate contact region CGMA22 and D_PW as well as CGMA27 and D_NW are required to be arranged complying with a spacing rule between a gate pattern and an active region. As a result, a layout area increases in the y direction in the figure. In addition, in order to secure a yield, it is desired to arrange two or more contacts between metal and gates as much as possible. However, in all the gate contact regions other than GCMA20, 21, and 23, it is impossible to arrange two contacts because of design rules between metals, gate patterns, and the like around the gate contact regions and restriction in terms of an area.
As opposed to FIG. 35, FIG. 36 is a diagram in which a contact CM between the one-layer metal and the two-layer metal is arranged on CGMA20, 21, 24, and 25 and CGMA20 and 21 as well as CGMA24 and 25 are connected by the two-layer metal M2. Therefore, when global wiring is made by two layers of metal on such a layout, it is likely that an area increases because of these wirings.
As described above, in the conventional layout design method, dummy gates having a length matching a gate electrode with a largest gate width are formed to be arranged over both ends in a gate width direction of gate electrodes of all transistors. Thus, positions where gate patterns and gate contact regions connecting with the gate electrodes can be arranged are restricted by a minimum spacing rule between the gate contact regions and the dummy gates. As a result, it is inevitable to reduce the number of contacts or a layout area increases.
In addition, in the arrangement of the gate contact regions, it is necessary to consider a design rule between the gate contact regions and the dummy gates and a metal wiring connecting with the gate contact regions. Thus, layout design is complicated and a design man-hour increases compared with the conventional semiconductor device without dummy gates. In many signal wirings, it is necessary to consider an influence of an area an influence among signals. When wiring correction due to the influences occurs, since it is necessary to consider a design rule for the dummy gates with respect to original layout design, design is complicated and a design man-hour further increases.
In order to place a layout within a predetermined pitch, if transistors and dummy gates are arranged to be placed within the pitch in an initial stage and contact regions and metal wirings are set to match the arrangement, when a design rule cannot be met once, it is likely that all the transistors, dummy gates, contacts, and wirings have to be moved and corrected in the worst case. In such a case, a design back tracking man-hour is large. As a method to avoid such a case, it is possible to change the number of contacts to be arranged from two to one. It is recommended not to take such an avoidance method if possible from the viewpoint of improving a yield.
As described above, the conventional layout design method for semiconductor devices includes many factors causing an increase in an area and a design man-hour or a decline in a yield in arranging dummy gates.